David Jeffrey Ljung Madison

Programming, Algorithm Design/Development, VLSI / CPU Verification

Version Info

Resume v4.4, released 2011-02-24.
Please get current source at: http://Daveola.com/Resume/

Contact Info

Before contacting me, make sure you have an up-to-date resume. Please don't contact me about full-time work, I'm a contractor.
I'm also not interested in any long-term relocating.

Recruiters: Use email, DO NOT CALL
Home: 415.341.5555 (call between 12-8p PST)
Email:

Objective

To experience an incredible life.

Work Experience

Director of Verification, iCelero, LLC. Jul 2007 - Present.

(Previously "3 Plus 1, Corp")

Managed verification for a complex, fully-custom processor under a very tight schedule
Created complete toolchain and testbenches for entire CPU verification process, from block level to full-chip to SOC.
Created highly sophisticated test packer/generator for VLIW CPU

Independent Consultant, DaveSource Consulting. Jul 2002 - Present.

Contractor for VLSI/Processor Verification and/or software design/implementation.
I'm not terribly interested in full-time employment right now.
Some of the kind of things I've worked on:

Full CPU verification
Formal verification tool development.
Designed and implemented operations management algorithms under very tight schedules. Invented techniques that returned an order of magnitude improvement in runtime and savings.
Custom image sorting software.
Custom web applications.

CPU Verification Engineer, Transmeta Corp. Jan 2000 - Jul 2002.

I split my time between tool development and block-level verification:

Created cycle-accurate models (verilog, perl, scheme) of blocks for testing/debug/verif as well as a fake front-end and testbench creation tool.

Created testbenches for formal verification for a number of blocks.

Wrote pseudo-directed random test generators (verilog, scheme).

Accomplished such high coverage for blocks on final project (due to formal verification and test generators) that all bugs were found pre-silicon.

CPU Verification Engineer, SandCraft Inc.. Jul 1998 - Jan 2000.

I was part of a MIPs processor verification team.

In charge of initial verification of the execute half of SR1/Montage CPU:: Designed and implemented testbench in Behavioral Verilog/C PLI. Initially it tested portions of the chip that were finished, and eventually was used for full chip verification.
Created the major tool flow for verification except for some random code generators and the simulator.
Wrote an assembler/template generator and a weightfile generator
Wrote testplan, found and debugged failures with logic designers
Wrote queueing software, status scripts, plenty of docs
Preparation for next project (SR1-GX):

Used down time to rewrite a large portion of the tool chain and documentation to clean it up and add desired features.
Preparation for next project (SR1-GX):: Used down time to rewrite a large portion of the tool chain and documentation to clean it up and add desired features.

CPU Verification and Debug, VLSI Technology Lab, Hewlett-Packard. Aug 1994 - Jun 1998.

I was working in the Engineering Systems Lab (now SVTD) in Fort Collins, Colorado which designed the PA-RISC line of workstation/server processors.

PA-8000 (PCXU/Onyx) post-silicon debugging/tools:: Boot code and test framework
Hardware environmental testing and debug software
Finding and debugging failures
PA-8500 (Cuda) pre-silicon verification:

Random code generators, test creation
Test checkers and evaluators
Tools writer
PA-8500 post-silicon setup:

Created the entire tool chain for post-silicon system debug from scratch (except for some of the random code generators), such as controller scripts, environment scripts, shmoo scripts, failure searching and evaluation, boot code and test framework.
Other duties:

Lab Resource: Unix, programming, scripting..
Tool geek (wrote CAD tools, personnel tools, etc..)
PA-8500 (Cuda) pre-silicon verification:: Random code generators, test creation
Test checkers and evaluators
Tools writer
PA-8500 post-silicon setup:

Created the entire tool chain for post-silicon system debug from scratch (except for some of the random code generators), such as controller scripts, environment scripts, shmoo scripts, failure searching and evaluation, boot code and test framework.
Other duties:

Lab Resource: Unix, programming, scripting..
Tool geek (wrote CAD tools, personnel tools, etc..)
PA-8500 post-silicon setup:: Created the entire tool chain for post-silicon system debug from scratch (except for some of the random code generators), such as controller scripts, environment scripts, shmoo scripts, failure searching and evaluation, boot code and test framework.
Other duties:

Lab Resource: Unix, programming, scripting..
Tool geek (wrote CAD tools, personnel tools, etc..)
Other duties:: Lab Resource: Unix, programming, scripting..
Tool geek (wrote CAD tools, personnel tools, etc..)

Shareware Programmer, Marginal Hacks

I maintain a bunch of tools that I wrote at Marginal Hacks.

album, the most popular project on there, is highly ranked at freshmeat and is the first link if you search for the word album at google, due to it's popularity.

Shareware Programmer, WizPort Project June 1993 - Current.

In college I spent a number of years creating a large software project called the WizPort, a solution to a very complex UNIX problem. The goal of the WizPort was to allow non-root level users set up a virtual UNIX machine that people could connect to on a different port. This 'machine' had it's own filesystem with a file security system that was far more complex and flexible than the UNIX system. Part of this project included creating an entirely new UNIX shell and modifying many UNIX utilities to work with the WizPort.

Project references available on request

University Project, DEStiny 1994

One of my favorite school projects was the DEStiny chip. This was a VLSI implementation of the DES password encryption algorithm that I created with a fellow student to demonstrate weaknesses in current password security.

Coolest Two Lines of Code Ever, SpeedWaller 1989

See the description at http://DaveSource.com/Projects/SpeedWaller.
6 months on two lines of code. Talk about dedication!

Publications

CPU electrical verification, August 1997, HP Journal (as "David J. Ljung") [local copy]
CPU Block verification using formal tools

Skills

Computer Languages: I write most of my big programs in C, Perl or Java, though I have written large projects in Assembly and Verilog. I have worked in C++, but not for a while. Our test environment at Transmeta was in Scheme.
At one time I've even used the following languages: Lisp, Basic, Fortran, Ruby, Python, sed, yacc, sh, ksh, zsh, csh, tcsh, and so forth.
I generally require only two days to learn a new language, and I gain fluency soon thereafter.
Computing Environments: I have experience in UNIX system administration/shell scripting and have expertise in UNIX programming.
Human Languages: I read and write English fluently. I am a firm believer in writing understandable documentation and I have been known to over-comment my code.
Breaking things: I like to use things in new and interesting ways, I believe this makes me a good verification engineer. I have managed to break and find bugs in almost every tool I have used, including some of the big guys:
gcc, cpp preprocessor (a hang!), HPUX CC, HPUX linker, various assemblers, perl (2 so far), various shells (tcsh, ksh, ..), various verilog simulators (VCS, ESP), rccs versioning software, etc..

Education

Degree: B.S. ECE/CS (Double major: Electrical Computer Engineering with Computer Option and Computer Science)

School: 1989-1994: University Of Wisconsin, Madison

Personal

When I'm not programming geeky things, I love to cook, ski and play with the many animals who live with me. I spend most of my free time Swing Dancing.

Member, DNRC

Time's Person of the Year, 2006